The present invention relates to a semiconductor device, and more particularly to a thin film transistor formed on an insulating substrate.
A thin film transistor (hereinafter referred to as "TFT") using a semiconductor film which is formed on an insulating substrate is used for various purposes. In a case where a multiplicity of TFT's are integrated on a monocrystalline semiconductor film, a circuit for operating the TFT's does not include the capacitance between the semiconductor film and an insulating substrate for supporting the semiconductor film, and hence the TFT's can operate at a higher speed, as compared with an integrated circuit which is formed in a bulk semiconductor substrate through the well-known separation technique using a pn junction. Further, when a polycrystalline or amorphous semiconductor film is used in place of the monocrystalline semiconductor film, a thin film semiconductor device can be formed at a reduced temperature. For example, a thin film transistor array has been formed on a glass or quartz substrate, to be used in a liquid crystal display device. An example of a thin film semiconductor device which is formed by using the above-mentioned low-temperature process, is described in an article entitled "Thin-film transistors on molecular-beam-deposited polycrystalline silicon" by M. Matsui et al. (J. Appl. Phys., Vol. 55, No. 6, 1984, pages 1590 through 1595). However, such a prior art has drawbacks. In order to clearly show the drawbacks of the prior art, a method of fabricating a conventional thin film semiconductor device by using the low-temperature process will be explained below, by reference to FIGS. 1A to 1D.
Referring to FIG. 1A, a polycrystalline silicon film 2 having a thickness of 0.5 to 1 .mu.m is formed on a glass substrate 1 by a chemical vapor deposition (CVD) method or the vacuum deposition method, and is selectively etched by photolithography so as to have the form of an island. Then, as shown in FIG. 1B, a silicon oxide film 3 which has a thickness of about 2,000.ANG. and serves as a gate insulating film, and a polycrystalline silicon film 4 which has a thickness of about 5,000.ANG. and serves as a gate material, are formed by a CVD method. Next, the silicon oxide film 3 and the gate polycrystalline silicon film 4 are selectively etched as shown in FIG. 1C. Then, phosphorous ions accelerated by an accelerating voltage of 100 KeV impinge upon the silicon island 2, to implant phosphorous in the silicon island 2 at a dose rate of 1.times.10.sup.16 cm.sup.-2, thereby forming source and drain regions in the silicon island 2. Thereafter, as shown in FIG. 1D, a protective film 5 having a thickness of about 5,000.ANG. is formed by a CVD method, and the structure thus obtained is then kept at 550.degree. C. for 10 hours, to activate phosphorous implanted in the silicon island 2 and to make the protective film 5 dense. Usually, the softening temperature of the glass substrate 1 is about 600.degree. C. In order to carry out the above heat treatment without deforming the glass substrate 1, it is necessary to make the temperature of the heat treatment less than 600.degree. C. Accordingly, it takes a lot of time to activate phosphorous implanted in the silicon island 2. Further, the use of the ion implantation method will increase the manufacturing cost of the device.
In other words, n-type, highly-doped regions 6a and 6b serving as source and drain regions are completely formed by the above heat treatment, and will be kept in low-resistance contact with an electrode material. Next, apertures for contact are formed in the protective film 5, and then a source electrode 7a and a drain electrode 7b each made of aluminium are deposited on the protective film 5, to be kept in contact with the source region 6a and the drain region 6b, respectively, through the apertures of the protective film 5. Thus, a TFT is completed. When a positive voltage is applied to the gate film 4 of the above TFT, an n-channel layer is formed in a channel region 6c of the silicon island 2 which exists between the source region 6a and the drain region 6b, and thus the TFT is put in an ON-state. When no voltage is applied to the gate film 4, the inherent (intrinsic) resistance of the channel region 6c is connected between the source region 6a and the drain region 6b, and thus the TFT is put in an OFF-state.
As explained above, according to the conventional low-temperature process using the ion implantation method, the cost for forming the source and drain regions becomes high, and moreover it takes a lot of time to activate implanted ions.